1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device in which data can be electrically reprogrammed.
2. Background Art
Semiconductor memory devices of recent years tend to increase the number of bits (the number of memory cells) to increase the amount of data programmed to one chip. Therefore, in recent years, many semiconductor memory devices are proposed having structures in which memory cells are disposed three dimensionally (hereinbelow referred to as “3D laminated cell structures”) to increase the integration of memory (refer to JP-A 2007-266143 (Kokai), U.S. Pat. No. 5,599,724, and U.S. Pat. No. 5,707,885).
In an EEPROM using a high voltage for programming and the like, an HV transistor is indispensable to breakdown against the high voltage. However, it is difficult to reduce the programming voltage, and the HV transistor cannot shrink. In the case where, for example, an HV transistor is used as a transfer gate transistor connected to a word line, it is necessary that the number of transistors is the same as the number of word lines. Accordingly, it is difficult to reduce the occupied surface area of the entire chip due to the occupied surface area of the HV transistor. In particular, the occupied surface area of the HV transistor becomes a problem in the case where a 3D laminated cell structure is formed.
In a NAND flash memory, for example, using a floating gate as the memory layer and a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) nonvolatile semiconductor memory device using silicon nitride and the like as the memory layer, laminating the memory cell portion may be considered to increase the memory density. JP-A 2007-180389 (Kokai) discusses technology in regard to a laminated nonvolatile semiconductor memory device that includes multiple memory cell strings in which a semiconductor is formed in a pillar configuration perpendicular to a semiconductor substrate and multiple memory cells are connected in series.
In the nonvolatile semiconductor memory device, a control gate of the memory cell is connected to a word line; the word line is drawn out to a peripheral circuit region; and a prescribed operation is performed. Then, the word line is provided at a density according to the arrangement density of the memory cells. On the other hand, although a transfer gate transistor is provided in the peripheral circuit region, generally, the size of the transfer gate transistor is larger than the distance between the word lines. Although multi-layered interconnections are formed by the word lines connected to the control gates of each cell in a laminated nonvolatile semiconductor memory device having multi-layered memory cells, technology is not known that connects each word line laminated in such multiple layers to the transfer transistor of the peripheral circuit region. Therefore, in conventional art, it is necessary to increase the spacing between laminated word lines, resulting in an impediment to shrinking and increased densities of nonvolatile semiconductor memory devices.